{"id":20445,"date":"2025-08-06T15:41:27","date_gmt":"2025-08-06T07:41:27","guid":{"rendered":"https:\/\/www.tosunai.com\/?page_id=20445"},"modified":"2025-08-08T10:08:01","modified_gmt":"2025-08-08T02:08:01","slug":"lin-bus-conformance-test-system","status":"publish","type":"page","link":"https:\/\/www.tosunai.com\/en\/solutions\/lin-bus-conformance-test-system\/","title":{"rendered":"LIN Conformance Testing System"},"content":{"rendered":"
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\n\t\t\t\t\tA new one-stop automated testing experience<\/span>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
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TOSUN CAN (FD)\/LIN Conformance Testing System provides a complete in-vehicle network testing solution through hardware standardization, software platformization, and use case modularization architecture design.<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t

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Highly integrated, one-step testing<\/h2>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
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This system is based on TOSUN's independently developed bus analysis tools, jammers, and special chassis for conformance testing, combined with standard peripheral instruments and equipment such as programmable power supplies, oscilloscopes, and digital multimeters, to form a highly integrated conformance testing system.<\/p>

In terms of software, the test logic required by the specifications is implemented based on the TSMaster test script. Through program control calls to the hardware system, it fully supports the automated conformance testing and test analysis reports of the following three points for automotive parts LIN nodes.<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t

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      \n\t\t\t\t\t\tTurn on automated testing with one click.
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      \n\t\t\t\t\t\tEasy to expand, modify report templates, and add new applications in the future\t\t\t\t\t<\/p>\n\t\t\t\t\n\t\t\t<\/div>\n\t\t\t\n\t\t<\/div>\n\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t

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      Electrical Characteristics<\/strong><\/p>

      • Master\/slave node operating voltage range test,<\/li>
      • Master\/slave node overvoltage\/undervoltage test<\/li>
      • Master\/slave node undamaged power supply voltage range<\/li>
      • Ground offset test<\/li><\/ul>


        Physical Layer Signal Performance<\/strong><\/p>

        • Master\/slave node output level test<\/li>
        • Master\/slave node resistance test<\/li>
        • Master\/slave node signal slope test<\/li>
        • Master\/node explicit\/implicit level conversion time test<\/li><\/ul>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/details>\n\t\t\t\t\t\t
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          Sync & Identifier Field Timing<\/strong><\/p>

          • Master node synchronization interval field explicit level length test<\/li>
          • Node identification synchronization interval field explicit level length test<\/li>
          • Master node synchronization delimiter length test<\/li>
          • Node identification synchronization delimiter length range test<\/li><\/ul>


            Header Structure & Reception<\/strong><\/p>

            • Master node header length test<\/li>
            • Receive header length range test from node<\/li><\/ul>


              Bit Timing & Message Format<\/strong><\/p>

              • Master node baud rate and bit timing parameter test<\/li>
              • Master node baud rate compatibility test<\/li>
              • Master node verification method test<\/li>
              • Message DLC Test<\/li>
              • Bus message total length test<\/li><\/ul>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/details>\n\t\t\t\t\t\t
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                Master node management test<\/strong><\/p>

                • Sleep processing test
                  • Master node sleep command frame transmission test<\/li>
                  • Master node initialization time test<\/li><\/ul><\/li>
                  • Wake-up processing test
                    • Master node receives wake-up request signal test<\/li>
                    • Master node local event wake-up test<\/li><\/ul><\/li><\/ul>


                      Node Management Testing<\/strong><\/p>

                      • Sleep processing test
                        • Slave node receives sleep command frame test<\/li><\/ul><\/li>
                        • Wake-up processing test
                          • Slave node receives wake-up request signal test<\/li>
                          • Slave node sends wake-up request test, etc.<\/li><\/ul><\/li><\/ul>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/details>\n\t\t\t\t\t\t
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                            • Scheduling table scheduling sequence test<\/li>
                            • Scheduling table time slot test<\/li><\/ul>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/details>\n\t\t\t\t\t<\/div>\n\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
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                              Electrical Fault Tolerance<\/strong><\/p>

                              • DUT power\/ground loss test<\/li>
                              • Bus-to-ground short circuit test<\/li>
                              • Bus-to-power short circuit test<\/li><\/ul>


                                Protocol Fault Injection<\/strong><\/p>

                                • Master-slave node incomplete frame interference test<\/li>
                                • Master node PID parity check error test<\/li>
                                • Master node responds to stop bit error test<\/li>
                                • Data transmission interrupted by new Break\/Sync field<\/li>
                                • Checksum and error testing, etc.<\/li><\/ul>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/details>\n\t\t\t\t\t\t
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